1. Technical Field The present disclosure relates to the field of semiconductor technology, and more particularly to a semiconductor device including a dummy device.
2. Description of the Related Art
In the field of semiconductor technology, a dummy device is often fabricated on a semiconductor device during the manufacturing process, so as to ensure uniform device density and to prevent pattern mismatch between devices.
In the past decade, embedded silicon germanium (e-SiGe) technology has been widely used to increase the mobility of p-type metal-oxide-semiconductor (PMOS) devices. As the technology process node scales from 28 nm to 22 nm and below, embedded silicon carbide (e-SiC) technology is more widely used in n-type metal-oxide-semiconductor (NMOS) with high-k metal gates.
The design and distribution of the dummy patterns on a stress layer is especially important when the technology process node is 22 nm and below. For example, improper design of the dummy patterns could result in overlay defects during subsequent processing, incompatibility with other semiconductor processes, and unreliable circuit simulation models (e.g. using Simulation Program with Integrated Circuit Emphasis (SPICE) models).
In some instances, the shape and layout between the dummy device and the transistors on the stress layer may differ significantly. As a result, during the manufacture of the semiconductor device, overlay defects and other problems may occur during subsequent processing, thereby impacting the yield and reliability of the semiconductor device.